Technical Specifications

Specifications & Highlights:

• Continuous, uninterrupted, receive coverage from 9KHz to 60MHz.
• 16bit ADC 
• Built-in Broadcast band Reject filter (can be bypassed)
• Intel Cyclone 10 FPGA
• Supports 2 fully independent receivers (sharing the same antenna - and with suitable PC software)
• Each receiver can display upto 1536kHz of spectrum
• Supports HPSDR Protocol 2 Firmware @ Gigabit speed
• Blocking Dynamic Range (ARRL Method) no detectable gain compression below ADC overload
• Transmit and receiver image rejection > 110dB
• Full duplex operation, any split over entire 160m to 6m range.
• Transmitter two-tone 3rd order IMD of -50dBc on 20m @ 10W PEP
• 20W RF output on 160 – 10m amateur bands, 10-15W on 6m
• Built-in high performance preamp, with a noise floor typically -135dBm in 500Hz
• Software-selectable 31dB input attenuator in 1dB steps
• High performance receiver –  (ie Dynamic Range typically 125dB)
• FPGA code can be updated via the Industry Standard TCP/IP network Ethernet connection
• Seven user-configurable open-collector outputs, independently selectable per band and Tx/Rx (for relay control, etc - with sequencing via PC code)
• Separate open-collector PTT connection for amplifier control, etc, with sequencer
• Microphone PTT jumper-selectable from tip or ring connection
• Bias for electret microphones via jumper
• Four user-configurable 12 bit analogue inputs (for ALC, SWR etc)
• Three user-configurable digital inputs (for linear amplifier over temperature, etc)
• Operate from a 13.8v DC supply